Intel® Stratix® 10 Embedded Memory User Guide

ID 683423
Date 10/01/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Give Feedback

4.4.6. FIFO2 Intel® FPGA IP Parameters

Table 59.  FIFO2 Intel® FPGA IP Core Parameters DescriptionThis table lists the parameters for the FIFO2 Intel® FPGA IP core.
Parameter Legal Values Description
What type of FIFO you prefer?
  • Single-clock
  • Dual-clock
Specifies the type of FIFO.
How wide should the FIFO be? Specifies the width of the data and q ports.
RAM block type
  • MLAB
  • M20K
Specifies the type of RAM Block used for FIFO
Parameter Settings: Reset Option
Enable Asynchronous Clear (ACLR) On/Off Specifies the write and read are reset asynchronously.
Parameter Settings: Performance Optimization
Enable per RAM block preserve/duplication for:
  • RAM write address *
  • RAM read address *

* Note: This will typically increase Fmax at the expense of resources.

On/Off Enables per RAM block preserve/duplication for:
  • RAM write address: Specifies whether RAM write address (and associated logic where appropriate) should be duplicated per RAM block.
  • RAM read address: Specifies whether RAM read address (and associated logic where appropriate) should be duplicated per RAM block.

    Note: This will typically increase MAX at the expense of resources.

When you select Dual-clock, the following options are available:
  • The synchronizer chain length for write gray-code pointer
  • The synchronizer chain length for read gray-code pointer
3, 4 Specify the multi-flop synchronizer chain length for write and read gray-code pointers.