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2.8. True Dual Port Dual Clock Emulator
This feature is supported only in the following conditions:
- Two read/write ports operation mode.
- Customize clocks for A and B ports clocking mode.
The TDP dual clock emulator consists of two DCFIFOs and a single RAM block. The DCFIFO handles clock domain crossing (CDC) issues for the control signals and is a temporary buffer for data storage before and after being processed by the RAM block.
Due to the non-deterministic latency caused by different clock frequencies, a valid signal is introduced to identify whether the output data is valid. When the valid signal is asserted, it indicates that you should adhere to the correct output data. If the valid signal is de-asserted, discard the output data.
|Signal||Intel® Arria® 10 TDP Dual Clock Mode||Intel® Stratix® 10 Emulated TDP Dual Clock Mode|
The clock connection to Port A must be a slow clock (clock A) and the clock connection to Port B must be a fast clock (clock B). Intel recommends the clock frequency ratio of clock B divided by clock A is greater than or equal to seven. This clock frequency ratio ensures a minimum latency of 5 clock cycle for Port A. The latency will not be guaranteed if the ratio is less than 7.
When you engage the TDP dual clock emulator feature, port A and port B will have different latency. The latency for port A decreases as the difference between the two clock frequencies increase, with a minimum latency of five clock cycles. Port B latency is fixed to two clock cycles, with the output registers always enabled for this configuration.
The following figures show the timing diagrams for the TDP dual clock emulator feature.
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