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4.2.2. eSRAM System Features
A given eSRAM system can achieve a maximum frequency of 750 MHz. The number of available eSRAM systems depends on the Intel® Stratix® 10 device in use.
Every memory channel within an eSRAM system has one write port and one read port, which can handle simultaneous read and write requests. Each channel has access to only its own banks, thus ensuring that each channel is independent from its neighbors.
The eSRAM system has an error correction code (ECC) which you can enable at the cost of some user-accessible data capacity. The ECC can improve data integrity by encoding write data with extended Hamming code and decoding read data for Single-bit Error Correction, Double-bit Error Detection (SECDED). Write latency and read latency are the same whether ECC is enabled or not.
There is a data coherency feature called Write Forwarding which you can enable to handle simultaneous write and read access to the same eSRAM memory location. The write data on the write port is forwarded to the read port and not read from the targeted SRAM bank. The write data is still written into the targeted eSRAM bank.
A low power mode can conserve static power at the cost of 1 clock cycle. In addition, each channel can power down unused banks, for additional power savings.
The eSRAM system includes a PLL which natively drives the clock domains necessary for eSRAM operation.
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