Low Latency Ethernet 10G MAC Intel® Cyclone® 10 GX FPGA IP Design Example User Guide

ID 683354
Date 11/30/2020
Document Table of Contents

4. Interface Signals Description

Use the following tables to find the description of the signals in the LL 10GbE MAC Intel® FPGA IP design examples. The pinout diagram for each design example specifies the width of the signals.

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