Low Latency Ethernet 10G MAC Intel® Cyclone® 10 GX FPGA IP Design Example User Guide

ID 683354
Date 11/30/2020
Public
Document Table of Contents

4.5. Status Interface

Table 14.   Status Interface Signals
Signal Direction Description

block_lock

Out Asserted when the link synchronization is successful.

channel_ready

channel_tx_ready

channel_rx_ready

tx_ready_export

rx_ready_export

Out Asserted when the channel is ready for data transmission.
atx_pll_locked Out Asserted when the TX PLL is locked.

Did you find the information on this page useful?

Characters remaining:

Feedback Message