1. Quick Start Guide 2. 10GBASE-R Ethernet Design Example for Intel® Cyclone® 10 GX Devices 3. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example for Intel® Cyclone® 10 GX Devices 4. Interface Signals Description 5. Configuration Registers Description 6. Low Latency Ethernet 10G MAC Intel® Cyclone® 10 GX FPGA IP Design Example User Guide Archives 7. Document Revision History for the Low Latency Ethernet 10G MAC Intel® Cyclone® 10 GX FPGA IP Design Example User Guide
You can compile and test the design in the supported Intel FPGA development kit.
- Launch the Intel® Quartus® Prime software and open the design example project file. Select Processing > Start Compilation to compile the design example.
The timing constraints for the design example and the design components are automatically loaded during compilation.
- Connect the development board to the host computer.
- Launch the Clock Controller application, which is part of the development kit, and set new frequencies for the design example.
Note: For the frequencies to set, refer to the Hardware Testing section in the respective design example chapter.
- In the Intel® Quartus® Prime software, select Tools > Programmer to configure the FPGA on the development board using the generated .sof file.
- Reset the system by pressing the PB0 push button.
- In the Intel® Quartus® Prime software, select Tools > System Debugging Tools > System Console to launch the system console.
- Change the working directory to <Example Design>\hwtesting\system_console.
- Initialize the design command list by running this command: source main.tcl.
Note: For a design example that does not provide the main.tcl file, refer to the Hardware Testing section in the respective design example chapter.
You can now run any of the predefined hardware tests from the System Console.
Observe the test results displayed.
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