Low Latency Ethernet 10G MAC Intel® Cyclone® 10 GX FPGA IP Design Example User Guide

ID 683354
Date 11/30/2020
Public
Document Table of Contents

3.7. Configuration Registers

You can access the 32-bit configuration registers of the design components through the Avalon® memory-mapped interface.

Table 9.  Register Map
Byte Offset Block
0x00_0000 Reserved
Channel 0
0x02_0000 Reserved
0x02_4000 PHY
0x02_6000 Native PHY Reconfiguration
0x02_8000 MAC
Channel 1
0x03_0000 Reserved
0x03_4000 PHY
0x03_6000 Native PHY Reconfiguration
0x03_8000 MAC
Traffic Controller
0x10_0000 Traffic Controller

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