Low Latency Ethernet 10G MAC Intel® Cyclone® 10 GX FPGA IP Design Example User Guide

ID 683354
Date 11/30/2020
Public
Document Table of Contents

4.4. PHY Interface Signals

Table 13.  PHY Interface Signals
Signal Direction Description
rx_serial_data In RX serial input data
tx_serial_data Out TX serial output data

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