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1. Quick Start Guide
2. 10GBASE-R Ethernet Design Example for Intel® Cyclone® 10 GX Devices
3. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example for Intel® Cyclone® 10 GX Devices
4. Interface Signals Description
5. Configuration Registers Description
6. Low Latency Ethernet 10G MAC Intel® Cyclone® 10 GX FPGA IP Design Example User Guide Archives
7. Document Revision History for the Low Latency Ethernet 10G MAC Intel® Cyclone® 10 GX FPGA IP Design Example User Guide
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2.7. Configuration Registers
You can access the 32-bit configuration registers of the design components through the Avalon® memory-mapped interface.
Byte Offset | Block |
---|---|
0x0000_0000 – 0x0001_CFFF | Reserved |
0x0001_D000 – 0xFFFF_FFFF | Client Logic |
Channel 0 | |
0x0000_0000 | MAC |
0x0000_8000 | PHY |
0x0000_d400 | RX SC FIFO |
0x0000_d600 | TX SC FIFO |
0x0000_c000 | Packet Generator and Checker |
Channel 1 | |
0x0001_0000 | MAC |
0x0001_8000 | PHY |
0x0001_d400 | RX SC FIFO |
0x0001_d600 | TX SC FIFO |
0x0001_c000 | Packet Generator and Checker |
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