Low Latency Ethernet 10G MAC Intel® Cyclone® 10 GX FPGA IP Design Example User Guide

ID 683354
Date 11/30/2020
Public
Document Table of Contents

4.1. Clock and Reset Interface Signals

Table 10.   Clock and Reset Interface Signals
Signal Direction Width Description

csr_clk

In 1 125-MHz configuration clock for the Avalon® memory-mapped interface.
ref_clk_clk In 1 322.265625-MHz clock for the TX PLL.
core_clk_312 Out 1 312.5-MHz clock for the fast domain.
core_clk_156 Out 1 156.25-MHz clock for the slow domain.
master_reset_n In 1 Assert this asynchronous and active-low signal to reset the whole design example.
csr_rst_n In 1 Active-low reset signal for the Avalon® memory-mapped interface.
tx_rst_n In 1 Active-low reset signal for the TX datapath.
rx_rst_n In 1 Active-low reset signal for the RX datapath.
tx_digitalreset In [NUM_CHANNELS] Asynchronous and active-high signal to reset PCS TX portion of the transceiver PHY.
rx_digitalreset In [NUM_CHANNELS] Asynchronous and active-high signal to reset PCS RX portion of the transceiver PHY.
tx_analogreset In [NUM_CHANNELS] Asynchronous and active-high signal to reset PMA TX portion of the transceiver PHY.
rx_analogreset In [NUM_CHANNELS] Asynchronous and active-high signal to reset PMA RX portion of the transceiver PHY.