Serial Lite III Streaming Stratix® V FPGA IP Design Example User Guide

ID 683335
Date 11/01/2021
Document Table of Contents

1.3.1. Procedure

This is a general procedure on how to generate the design example.

To generate the design example from the IP parameter editor:

  1. In the IP Catalog (Tools > IP Catalog), locate and select SerialLite III Streaming. The IP parameter editor appears.
  2. Specify a top-level name and the folder for your custom IP variation, and the target device. Click OK.
  3. Select a design from the Presets library. When you select a design, the system automatically populates the IP parameters for the design.
    Note: If you select another design, the settings of the IP parameters change accordingly.
  4. Under the Example Design tab, specify the design example parameters as described in Design Example Parameters.
    Note: At least one of the Simulation and Synthesis check boxes from File Types Generated must be selected to allow generation of Example Design files (Step 7).
  5. For Target Development Kit, select Stratix® V GX Transceiver Signal Integrity Development Kit.
  6. Click the Finish button. The Generation window appears.
  7. If you wish to generate design example, select the Generate Example Design option.
  8. Click the Generate button. The IP parameter editor generates the files for your IP variation according to your specifications. Click Exit if prompted when when generation is complete.
The software generates all design files in the sub-directories. These files are required to run simulation, compilation, and hardware testing.