Serial Lite III Streaming Stratix V FPGA IP Design Example User Guide

ID 683335
Date 11/01/2021
Public
Document Table of Contents

2. Detailed Description for Stratix® V Serial Lite III Streaming Standard Clocking Mode

These design examples demonstrate the functionalities of data streaming using standard clocking mode.

To generate the design examples, select the following preset(s):
  • Standard Clocking Mode 2x10G
By default, the design examples are generated as duplex core. To generate the design examples in simplex core, select Source or Sink for the Direction parameter.

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