Serial Lite III Streaming Stratix® V FPGA IP Design Example User Guide

ID 683335
Date 11/01/2021
Document Table of Contents

2.3. Functional Description

The design examples consist of various components. The following block diagrams show the design components and the top level connections of the design examples.

Figure 7. Design Example for Simplex Core in Standard Clocking Mode
Figure 8. Design Example for Duplex Core in Standard Clocking Mode