Serial Lite III Streaming Stratix® V FPGA IP Design Example User Guide

ID 683335
Date 11/01/2021
Document Table of Contents

2.5.2. Error Details

These are the list of supported errors in the design example.
Table 5.  List of Error Details
Error Description
Source Error:
Adaptation FIFO Overflow To indicate source adaptation FIFO overflow error.
Sink Errors:
Adaptation FIFO Overflow To indicate sink adaptation FIFO overflow error.
Loss of Alignment During Normal Operation To indicate loss of alignment error (error_rx[1]).
Meta Frame CRC Errors To indicate CRC errors.
Lane Swap Errors To indicate lane swap errors in traffic checker.
Lane Sequence Errors To indicate lane sequence error in traffic checker.
Lane Alignment Errors To indicate lane alignment error in traffic checker.