Serial Lite III Streaming Stratix® V FPGA IP Design Example User Guide

ID 683335
Date 11/01/2021
Document Table of Contents

3. Detailed Description for Stratix® V Serial Lite III Streaming Advanced Clocking Mode

These design examples demonstrate the functionalities of data streaming using advanced clocking mode.

To generate the design examples, select the following preset(s):
  • Advanced Clocking Mode 2x10G
By default, the design examples are generated as duplex core. To generate the design examples in simplex core, select Simplex for the Source or Sink parameter.