Serial Lite III Streaming Stratix® V FPGA IP Design Example User Guide

ID 683335
Date 11/01/2021
Document Table of Contents

3.5. Hardware Testing

Once you download the design and accompanying software into the FPGA, you can test the design operation through the interactive session. The interactive session provides helpful statistics, as well as controls for controlling various aspects of the design.

You can control the following operations through the interactive session by entering the option numbers listed below:

  1. Enable Data Generator/Checker—Enables the traffic generator and start sending out data. This option enable data streaming in continuous mode.
  2. Disable Data Generator/Checker—Disables traffic generation.
  3. Reset Source Core—Resets the source core and traffic generator.
  4. Reset Sink Core—Resets the sink core and traffic checker.
  5. Display Error Details—Displays the error statistics.
  6. Toggle Burst/Continuous Mode—Resets the source and sink MACs and switches the traffic generator to generate a burst or continuous traffic stream. By default, the design example is set to burst mode. When in continuous mode, the burst count will always show 1. Disable the data generator/checker before switching mode to avoid transmission error.
  7. Toggle CRC Error Insertion—Turns CRC error injection off or on. By default, the design example has CRC error injection turned off.