Serial Lite III Streaming Stratix V FPGA IP Design Example User Guide

ID 683335
Date 11/01/2021
Document Table of Contents

1.4.1. Procedure

To compile and simulate the design:
  1. Change the working directory to <example_design_directory>example/ed_sim/<simulator>.
  2. Run the simulation script for the simulator of your choice.
    Simulator Command
    ModelSim* do run_tb.tcl
    VCS* / VCS* MX sh
    Aldec* do run_tb.tcl
    NCSim sh
    A successful simulation ends with the following message, "Test Passed."
After successful completion, you can analyze the results.

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