Serial Lite III Streaming Stratix® V FPGA IP Design Example User Guide

ID 683335
Date 11/01/2021
Document Table of Contents

3.3.1. Design Example Components

The design example consists of following components:

  • Serial Lite III Streaming IP core variation
  • Source user clock—fPLL
  • Traffic generator
  • Traffic checker
  • Demo control
  • Demo management
  • Nios II processor code