Serial Lite III Streaming Stratix® V FPGA IP Design Example User Guide

ID 683335
Date 11/01/2021
Document Table of Contents

2.1. Features

Features for Standard Clocking Mode 2x10G design example includes:
  • Support 2 lanes with 10Gpbs transceiver data rate
  • Support simplex and duplex transmission modes
  • Traffic checker for data verification and lane de-skew verification
  • Support CRC error injection using Nios II processor