Serial Lite III Streaming Stratix V FPGA IP Design Example User Guide

ID 683335
Date 11/01/2021
Document Table of Contents
Give Feedback

1.1. Directory Structure

The Intel® Quartus® Prime software generates the design example files in the following folders:

  • <user_defined_design_example_directory>/seriallite_iii_sv/ed_sim
  • <user_defined_design_example_directory>/seriallite_iii_sv/ed_synth
  • <user_defined_design_example_directory>/seriallite_iii_sv/ed_hwtest

The following diagrams show the directories that contain the generated files for the design examples.

Figure 2. Directory Structure for Stratix® V Serial Lite III Streaming Design Example
Table 1.  Directory and File Description for Design Example Folder
Directory/File Description
ed_sim/tb_components The folder that contains the testbench files.




ed_sim/synopsys/vcs or ed_sim/synopsys/vcsmx

The folder that contains the simulation script. It also serves as a working area for the simulator.


The folder that contains the design example simulation source files.
ed_synth/seriallite_iii_streaming_demo.qpf Quartus project file.
ed_synth/seriallite_iii_streaming_demo.qsf Quartus settings file.
ed_synth/seriallite_iii_streaming_demo.sdc Synopsys Design Constraints (SDC) file.
ed_synth/src The folder that contains the design example synthesizable components.
ed_synth/src/seriallite_iii_streaming_demo.v Design example top-level HDL.


Design example DUT top-level files.


The folder for each synthesizable component including Qsys generated IPs, such as demo_mgmt and demo_control.
ed_hwtest The folder that contains the design example hardware setup files.
ed_hwtest/Readme.txt Instruction file to download the generated design example on the development kit.
ed_hwtest/ A script to generate demo control and PLL IPs with NIOS II processor.
ed_hwtest/master_export.v User interface Verilog design file.
ed_hwtest/master_export_hw.tcl Component description file for master export custom IP.
ed_hwtest/software The folder that contains scripts to download the demo_control program into NIOS II processor and open an interactive terminal to run the design example.