Serial Lite III Streaming Stratix® V FPGA IP Design Example User Guide

ID 683335
Date 11/01/2021
Document Table of Contents

1.5. Compiling and Testing the Design

The Serial Lite III Streaming IP core parameter editor allows you to compile and run the design example on a target development kit.

Follow these steps to compile and test the design in hardware:

  1. Launch the Intel® Quartus® Prime software and change the directory to /ed_synth/ and open the seriallite_iii_streaming_demo.qpf file.
  2. Click Processing > Start Compilation to compile the design.

    The timing constraints for the design example and the design components are automatically loaded during compilation.

  3. Connect the development board to the host computer.
  4. Configure the FPGA on the development board using the generated .sof file (Tools > Programmer).

The design examples target the Stratix® V Transceiver Signal Integrity Development Kit.

The design includes an SDC script as well as a QSF with verified constraints in loopback mode. If you use the design example with another device or development board, you may need to update the device setting and constraints in the QSF file.

You must use correct pin constraints when using the core in simplex mode or when using more than one reconfiguration controller. The synthesized design typically includes a reconfiguration interface for at least three channels because three channels share an Avalon® memory-mapped interface, which connects to the Transceiver Reconfiguration Controller IP core. Conversely, you cannot connect three channels that share an Avalon® memory-mapped interface to different Transceiver Reconfiguration Controller IP cores or you will receive a Fitter error.