Serial Lite III Streaming Stratix® V FPGA IP Design Example User Guide

ID 683335
Date 11/01/2021
Public
Document Table of Contents
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3.3.1.1. Serial Lite III Streaming IP Core

The Serial Lite III Streaming IP core variation accepts data from the traffic generator and formats the data for transmission. It also receives data from the link, strips the headers, and presents it to the traffic checker for analysis. The core is generated using the parameter editor in the Intel® Quartus® Prime software.