Serial Lite III Streaming Stratix® V FPGA IP Design Example User Guide

ID 683335
Date 11/01/2021
Document Table of Contents

3.5.1. Design Setup

The design example targets the Stratix® V Transceiver Signal Integrity Development Kit.

The design includes an SDC script as well as a QSF with verified constraints in loopback mode. If you use the design example with another device or development board, you may need to update the device setting and constraints in the QSF file.

You must use correct pin constraints when using the core in simplex mode or when using more than one reconfiguration controller. The synthesized design typically includes a reconfiguration interface for at least three channels because three channels share an Avalon® memory-mapped slave interface, which connects to the Transceiver Reconfiguration Controller IP core. Conversely, you cannot connect three channels that share an Avalon® memory-mapped interface to different Transceiver Reconfiguration Controller IP cores or you will receive a Fitter error.