Video and Vision Processing Suite Intel® FPGA IP User Guide

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ID 683329
Date 4/04/2022
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Document Table of Contents
Document Table of Contents x
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. Chroma Resampler Intel® FPGA IP 10. Clipper Intel® FPGA IP 11. Clocked Video to Full Raster Converter Intel® FPGA IP 12. Color Space Converter Intel® FPGA IP 13. Full Raster to Clocked Video Converter Intel® FPGA IP 14. Full Raster to Streaming Converter Intel® FPGA IP 15. Guard Bands Intel® FPGA IP 16. Mixer Intel® FPGA IP 17. Pixels in Parallel Converter Intel® FPGA IP 18. Scaler Intel® FPGA IP 19. Tone Mapping Operator Intel® FPGA IP 20. Test Pattern Generator Intel® FPGA IP 21. Video Frame Buffer Intel® FPGA IP 22. Video Streaming FIFO Intel® FPGA IP 23. Warp Intel® FPGA IP 24. Design Security 25. Document Revision History for Video and Vision Processing Suite User Guide
1. About the Video and Vision Processing Suite x
1.1. Device Family Support 1.2. Video and Vision Processing IPs Release Information 1.3. Video and Vision Processing IPs Features 1.4. Lite versus Full IP Variants 1.5. Glossary of Video and Vision Terminology
2. Getting Started with the Video and Vision Processing IPs x
2.1. Video and Vision Processing IP Time-out Behavior 2.2. Generating a Video and Vision Processing IP 2.3. Simulating the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description x
3.1. Auxiliary Control Packets 3.2. Latency 3.3. IP Debugging Features 3.4. Stall Behavior and Error Recovery 3.5. Avalon Streaming Video Protocol Versus Intel FPGA Streaming Video Protocol
5. Video and Vision Processing IP Registers x
Parameterization registers Control and debug registers IP specific registers IPs without a memory mapped control interface 5.1. Video and Vision Processing IP Control Examples
7. Protocol Converter Intel® FPGA IP x
7.1. About the Protocol Converter IP 7.2. Protocol Converter IP Parameters 7.3. Protocol Converter IP Functional Description 7.4. Protocol Converter IP Interfaces 7.5. Protocol Converter IP Registers 7.6. Protocol Converter IP Software API
7.1. About the Protocol Converter IP x
7.1.1. Protocol Converter IP Performance and Resources
8. 3D LUT Intel® FPGA IP x
8.1. About the 3D LUT Intel® FPGA IP 8.2. 3D LUT IP Parameters 8.3. 3D LUT IP Block Description 8.4. 3D LUT IP Registers 8.5. 3D LUT IP Software API
8.1. About the 3D LUT Intel® FPGA IP x
8.1.1. 3D LUT IP Features 8.1.2. 3D LUT IP Performance IP and Resource Information
8.3. 3D LUT IP Block Description x
8.3.1. 3D LUT IP Interfaces 8.3.2. 3D LUT IP Latency
9. Chroma Resampler Intel® FPGA IP x
9.1. About the Chroma Resampler IP 9.2. Chroma Resampler IP Parameters 9.3. Chroma Resampler IP Functional Description 9.4. Chroma Resampler IP Registers 9.5. Chroma Resampler IP Software API
9.1. About the Chroma Resampler IP x
9.1.1. Chroma Resampler Performance and Resources
9.3. Chroma Resampler IP Functional Description x
9.3.1. Chroma Resampler IP Interfaces
10. Clipper Intel® FPGA IP x
10.1. About the Clipper IP 10.2. Clipper IP Parameters 10.3. Clipper IP Interfaces 10.4. Clipper IP Registers 10.5. Clipper IP Software API
10.1. About the Clipper IP x
10.1.1. Clipper IP Performance and Resources
11. Clocked Video to Full Raster Converter Intel® FPGA IP x
11.1. About the Clocked Video to Full Raster Converter IP 11.2. Clocked Video to Full Raster Converter Parameters 11.3. Clocked Video to Full Raster Converter Block Description 11.4. Clocked Video Converter to Full Raster IP Registers
11.1. About the Clocked Video to Full Raster Converter IP x
11.1.1. Clocked Video to Full Raster Converter Features 11.1.2. Clocked Video to Full Raster Converter Performance and Resources
11.3. Clocked Video to Full Raster Converter Block Description x
11.3.1. Clocked Video to Full Raster Converter Interfaces
12. Color Space Converter Intel® FPGA IP x
12.1. About the Color Space Converter IP 12.2. Color Space Converter IP Parameters 12.3. Color Space Converter IP Functional Description 12.4. Color Space Converter IP Registers 12.5. Color Space Converter IP Software API
12.1. About the Color Space Converter IP x
12.1.1. Color Space Converter IP Features 12.1.2. Color Space Converter IP Performance and Resources
12.3. Color Space Converter IP Functional Description x
12.3.1. Color Space Converter IP Interfaces
13. Full Raster to Clocked Video Converter Intel® FPGA IP x
13.1. About the Full Raster to Clocked Video Converter 13.2. Full Raster to Clocked Video Converter Parameters 13.3. Full Raster to Clocked Video Converter Block Description 13.4. Full Raster to Clocked Video Converter Registers
13.1. About the Full Raster to Clocked Video Converter x
13.1.1. Full Raster to Clocked Video Converter Features 13.1.2. Full Raster to Clocked Video Converter Performance and Resource Utilization
13.3. Full Raster to Clocked Video Converter Block Description x
13.3.1. Full Raster to Clocked Video Converter Interfaces
14. Full Raster to Streaming Converter Intel® FPGA IP x
14.1. About the Full Raster to Streaming Converter IP 14.2. Full Raster to Streaming Converter Parameters 14.3. Full Raster to Streaming Converter Block Description
14.1. About the Full Raster to Streaming Converter IP x
14.1.1. Full Raster to Streaming Converter Features 14.1.2. Full Raster to Streaming Converter Performance and Resources
14.3. Full Raster to Streaming Converter Block Description x
14.3.1. Full Raster to Streaming Converter Interfaces
15. Guard Bands Intel® FPGA IP x
15.1. About the Guard Bands IP 15.2. Guard Bands IP Parameters 15.3. Guard Bands IP Interfaces 15.4. Guard Bands IP Registers 15.5. Guard Bands IP Software API
15.1. About the Guard Bands IP x
15.1.1. Guard Bands IP Performance and Resources
16. Mixer Intel® FPGA IP x
16.1. About the Mixer IP 16.2. Mixer IP Parameters 16.3. Mixer IP Functional Description 16.4. Mixer IP Registers 16.5. Mixer IP Software API
16.1. About the Mixer IP x
16.1.1. Mixer IP Performance and Resources
16.3. Mixer IP Functional Description x
16.3.1. Mixer IP Interfaces
17. Pixels in Parallel Converter Intel® FPGA IP x
17.1. About the Pixels in Parallel Converter IP 17.2. Pixels in Parallel IP Converter Parameters 17.3. Pixels in Parallel Converter Interfaces 17.4. Pixels in Parallel Converter Registers 17.5. Pixels in Parallel Converter IP Software API
17.1. About the Pixels in Parallel Converter IP x
17.1.1. Pixels in Parallel IP Converter Performance and Resources
18. Scaler Intel® FPGA IP x
18.1. About the Scaler 18.2. Scaler IP Parameters 18.3. Scaler IP Functional Description 18.4. Scaler IP Registers 18.5. Scaler IP Software API
18.1. About the Scaler x
18.1.1. Scaler IP Performance and Resources
18.2. Scaler IP Parameters x
18.2.1. Updating Scaler IP Runtime Coefficients
18.3. Scaler IP Functional Description x
18.3.1. Scaler IP Interfaces
19. Tone Mapping Operator Intel® FPGA IP x
19.1. About the Tone Mapping Operator IP 19.2. TMO IP Parameters 19.3. TMO IP Block Description 19.4. TMO IP Registers 19.5. TMO IP Software API
19.1. About the Tone Mapping Operator IP x
19.1.1. TMO IP Features 19.1.2. TMO IP Performance and Resource Utilization
19.3. TMO IP Block Description x
19.3.1. TMO IP Interfaces 19.3.2. TMO IP Latency
20. Test Pattern Generator Intel® FPGA IP x
20.1. About the Test Pattern Generator IP 20.2. Test Pattern Generator IP Parameters 20.3. Test Pattern Generator IP Functional Description 20.4. Test Pattern Generator IP Registers 20.5. Test Pattern Generator IP Software API
20.1. About the Test Pattern Generator IP x
20.1.1. Test Pattern Generator IP Performance and Resources
20.3. Test Pattern Generator IP Functional Description x
20.3.1. Test Pattern Generator IP Interfaces
21. Video Frame Buffer Intel® FPGA IP x
21.1. About the Video Frame Buffer IP 21.2. Video Frame Buffer IP Parameters 21.3. Video Frame Buffer IP Functional Description 21.4. Video Frame Buffer IP Registers 21.5. Video Frame Buffer IP Software API
21.1. About the Video Frame Buffer IP x
21.1.1. Video Frame Buffer Performance and Resources
21.3. Video Frame Buffer IP Functional Description x
21.3.1. Video Frame Buffer IP Interfaces
22. Video Streaming FIFO Intel® FPGA IP x
22.1. About the Video Streaming FIFO IP 22.2. Video Streaming FIFO IP Parameters 22.3. Video Streaming FIFO IP Interfaces
22.1. About the Video Streaming FIFO IP x
22.1.1. Video Streaming FIFO IP Performance and Resources
23. Warp Intel® FPGA IP x
23.1. About the Warp IP 23.2. Warp IP Parameters 23.3. Warp IP Block Description 23.4. Warp IP Registers 23.5. Warp IP Software API
23.1. About the Warp IP x
23.1.1. Warp IP Features 23.1.2. Warp IP Performance and Resource Utilization
23.3. Warp IP Block Description x
23.3.1. Warp IP Interfaces 23.3.2. Warp IP Latency 23.3.3. External Memory for Warp IP
23.5. Warp IP Software API x
23.5.1. Using Warp IP Software 23.5.2. Warp IP Software Code Examples
24. Design Security x
24.1. Memory Subsystems 24.2. Considering Design Security
1. About the Video and Vision Processing Suite
2. Getting Started with the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description
4. Video and Vision Processing IP Interfaces
5. Video and Vision Processing IP Registers
6. Video and Vision Processing IPs Software Programming Model
7. Protocol Converter Intel® FPGA IP
8. 3D LUT Intel® FPGA IP
9. Chroma Resampler Intel® FPGA IP
10. Clipper Intel® FPGA IP
11. Clocked Video to Full Raster Converter Intel® FPGA IP
12. Color Space Converter Intel® FPGA IP
13. Full Raster to Clocked Video Converter Intel® FPGA IP
14. Full Raster to Streaming Converter Intel® FPGA IP
15. Guard Bands Intel® FPGA IP
16. Mixer Intel® FPGA IP
17. Pixels in Parallel Converter Intel® FPGA IP
18. Scaler Intel® FPGA IP
19. Tone Mapping Operator Intel® FPGA IP
20. Test Pattern Generator Intel® FPGA IP
21. Video Frame Buffer Intel® FPGA IP
22. Video Streaming FIFO Intel® FPGA IP
23. Warp Intel® FPGA IP
24. Design Security
25. Document Revision History for Video and Vision Processing Suite User Guide

5. Video and Vision Processing IP Registers

Each IP has an optional memory-mapped control agent interface. When you turn Memory-mapped control interface on in the GUI, the interface connects to your host processor via an Avalon memory mapped host interface (or via an AXI4 memory mapped bus through conversion in Platform Designer). It provides a unified method of controlling the IPs.

Every IP has a standard address map when you turn on Memory-mapped control interface. If you turn off Memory mapped control interface, the IP always processes video data when it is available.

In general, video and vision processing IP register maps have these distinctives areas:

  • A common area, which contains parameterization information. You can read from IPs to determine their parameters, which allows portability of software and binaries between different video and vision processing platforms.
  • An IP-specific video and vision processing area, which contains functional configuration information for the specific IP.
  • An optional control and debug register area, which allows you to write video field information in lite variants, read video field information in full variants, and to perform other control functions.

Control interfaces use Avalon memory-mapped interfaces. Platform Designer natively supports AXI4-Lite protocols and can automatically adapt to and from Avalon memory-mapped interfaces. Memory interfaces also use Avalon memory-mapped interfaces.

Table 8.  Register Map for Full Variant Video and Vision Processing IPsWith some exceptions (for example coefficient banks) in lite variants, register writes usually take effect at the start of the next field.
Address Register
Parameterization Registers
0x0000 VID_ID
0x0004 VERSION
0x0008 to 0x00FF IP-specific parameterization registers.
0x0100 to 0x011F Reserved for future use.

Reserved for optional Control and debug registers

0x0120 IMG_INFO_WIDTH
0x0124 IMG_INFO_HEIGHT
0x0128 IMG_INFO_INTERLACE
0x012C Reserved for future use.
0x0130 IMG_INFO_COLORSPACE
0x0134 IMG_INFO_SUBSAMPLING
0x0138 IMG_INFO_COSITING
0x013C IMG_INFO_FIELD_COUNT
IP specific registers
Read-only registers
0x0140 STATUS
0x0144 to RW_BASE Optional additional read-only registers
Read-write registers
RW_BASE Optional COMMIT register
RW_BASE+4 onwards Optional additional read-write registers

Parameterization registers

The parameterization registers address space occupies from the base address of the IP to a maximum address of 0x011F. The first two registers in this section are the product ID and version registers, so you can identify the IP and the structure of its register map.

The next registers are an optional set of further parameterization information which IPs may populate to inform software on how to control the IP.

For example, a clipper describes clipping using either offsets from the edge of the video or using a top-left corner offset with required height and width. Control software can interrogate the clipper’s parameterization registers to determine which is correct and drive clipping control register accesses accordingly. You can use the same control software across different video pipeline configurations.

The parameterization registers section is followed by an unused area from 0x0100 to 0x011F.

Control and debug registers

You control the IPs in two ways:

  • Provide the input video field information, for example the type of video packets you send to the IP with respect to height, width, or interlacing.
  • Instruct the IP, for example which clipper offsets, mixer offsets, or scaling behavior to apply.

Full variants send image information packets down the video processing pipeline to communicate video field information. Image information packets handle the communication of any resolution changes to downstream IPs. You can control IP functions for full variants via the IP specific registers.

Communicate video field information and control IP functions for lite variants via the control and IP specific registers, using the register interface.

Registers 0x0120 to 0x0138 (IMG_INFO_WIDTH to IMG_INFO_COSITING) are the image information registers. For lite variants, write to these to set the dimensions and properties of incoming video fields. For full variants, ignore these registers. However, if you turn on debug features, you can read these registers to retrieve details of the image information fields that the IP receives via the last received image information packet.

Register 0x013C is the IMG_INFO_FIELD_COUNT register. Read this register for full variants when you turn on Debug features for the field count field of the last received image information packet.

Register 0x0140 is the STATUS register. IPs hold the LSB of this register high while they process video packets. The LSB returns low in-between video fields. For full variants, bit 1 of this register is the pending register updates bit. The IP sets this bit when you make writes to the IP's register map. The IP automatically clears this bit.

The COMMIT register is at address RW_BASE or later. Write to this register after writing new values to any of the registers in the IP specific portion of the address map. The IP sets the pending register updates bit of the STATUS register in response and clears it when the new settings take effect.

IP specific registers

This section of the register map is different for every IP and comprises read and write registers required to control the IP, such as clipping or mixing offsets or color space or scaling coefficients.

IPs without a memory mapped control interface

If you turn off memory mapped control interface, the IP always processes video data when it is available.

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