Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 4/04/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

17.2. Pixels in Parallel IP Converter Parameters

Table 216.  Pixels in Parallel IP Converter Parameters
Parameter Allowed range Description
Video data format
Lite mode On or off Turn on to use the lite variant of the Intel FPGA Streaming Video protocol.
Bits per color sample 8 to 16 Select the number of bits per color sample.
Number of color planes 1 to 4 Select the number of color planes per pixel.
Input pixels in parallel 1 to 8 Select the number of pixels in parallel at the input interface.
Output pixels in parallel 1 to 8 Select the number of pixels in parallel at the output interface.
Datapath settings
Dual clock On or off Turn on to operate dual clocks.
FIFO depth 0, 32, 64, 128, 256, 1024, 2048 Specify the depth of the FIFO in words (beats of data). Select 0 to omit the FIFO entirely. The FIFO depth must be > 0 if you turn on Dual clock.
Control settings
Separate clock for control interface On or off Turn on to enable a separate clock for the control agent interface.
Debug features On or off Turn on to enable readback of frame info registers via the control agent interface.
Pipeline optimization
Pipeline ready signals On or off Turn on to add extra pipeline registers to the AXI4-S tready signals.