Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 4/04/2022

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14.3. Full Raster to Streaming Converter Block Description

The IP accepts full raster video input format as a full raster interface of pixel data and timing markers embedded in the TDATA bus of an AXI4-S interface. Also, the IP filters out the timing markers from the TDATA bus and provides a video-active only data format on the output interfaces that conforms to the Intel FPGA streaming video protocol specification.
Figure 33. Streaming Full Raster to Streaming Converter high-level block diagram.The figure shows the IP consists of two blocks: a full raster stripper and an asynchronous FIFO buffer.

The full raster stripper strips the full raster timing information from the AXI4-S full raster stream, leaving active-video data on the AXI4-S lite bus. The IP strips the timing information by setting the AXI4-S TVALID signal low during the blanking interval. When the input AXI4-S full raster bus sets its TUSER signal high, the IP is in blanking. The stripper holds the TUSER high until the IP transmits the first active pixel.

Figure 34. Streaming Full Raster to Streaming Converter Timing DiagramAn example of how the output TUSER signal is generated by detecting and holding the input TUSER signal on the full raster video domain, until the first active pixel is detected on the TDATA bus.

The full raster stripper has a pixel formatter logic, which is mainly based on a barrel shifter logic. It allows the IP to detect the correct position of the start of field for a pixel in parallel scenarios. It aligns the tdata packet content on the output video stream to ensure that the start of field always coincides with pixel 0.

The IP assumes that the transmitter side generates video data with a slower or faster pixel clock rate compared to the receiver video interface. Consequently, moving video data between two different clock domains requires clock domain crossings. Additionally, the TVALID and TREADY flow-controlled AXI4-S video interface may cause the following control-flow problems on the video datapath:

  • Clock-skew matching, if video receiver and transmitter and video processing clocks do not match.
  • In-rush of data if one of the modules in the video pipeline cannot offer the necessary throughput to move the data at the expected rate.

This IP includes an asynchronous output FIFO buffer that handles clock crossing domains between the full raster and video processing clock domains. Additionally, it temporally accepts data to accommodate a small amount of data-skew mismatching or in-rush data when transferring data between full raster and active-video only video interfaces.