Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 4/04/2022

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Document Table of Contents

8.1.1. 3D LUT IP Features

  • Avalon memory-mapped CPU interface for control and LUT upload
  • LUT sizes of 9³, 17³, 33³, and 65³
  • Tetrahedral interpolation
  • Range of 8 to 16 bits per color
  • Independent parameters for input, output, and LUT bits per color
  • Up to 8 pixels in parallel
  • Dynamic update of LUT via CPU interface
  • Double buffered LUT option allows for seamless run-time switching
  • Optional output alpha channel
  • Subframe fixed latency
  • Very small ALM footprint (~ 2K ALMs @ 2 pixels in parallel)