Visible to Intel only — GUID: wkp1619173411196
Ixiasoft
1. About the Video and Vision Processing Suite
2. Getting Started with the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description
4. Video and Vision Processing IP Interfaces
5. Video and Vision Processing IP Registers
6. Video and Vision Processing IPs Software Programming Model
7. Protocol Converter Intel® FPGA IP
8. 3D LUT Intel® FPGA IP
9. Chroma Resampler Intel® FPGA IP
10. Clipper Intel® FPGA IP
11. Clocked Video to Full Raster Converter Intel® FPGA IP
12. Color Space Converter Intel® FPGA IP
13. Full Raster to Clocked Video Converter Intel® FPGA IP
14. Full Raster to Streaming Converter Intel® FPGA IP
15. Guard Bands Intel® FPGA IP
16. Mixer Intel® FPGA IP
17. Pixels in Parallel Converter Intel® FPGA IP
18. Scaler Intel® FPGA IP
19. Tone Mapping Operator Intel® FPGA IP
20. Test Pattern Generator Intel® FPGA IP
21. Video Frame Buffer Intel® FPGA IP
22. Video Streaming FIFO Intel® FPGA IP
23. Warp Intel® FPGA IP
24. Design Security
25. Document Revision History for Video and Vision Processing Suite User Guide
Visible to Intel only — GUID: wkp1619173411196
Ixiasoft
2.2. Generating a Video and Vision Processing IP
To include the IP in a design, generate the IP in Platform Designer.
- Create a New Intel® Quartus® Prime project
- Open Platform Designer and create a project.
The video and vision processing IPs are only available in Platform Designer.
- Select DSP > Video and Vision Processing > <IP name> Intel® FPGA IP and click Add
- Enter a name for your IP variant and click Create.
The name is for both the top-level RTL module and the corresponding .ip file.The parameter editor for this IP appears.
- Choose your parameters.
- Click Generate HDL.
Intel® Quartus® Prime generates the RTL and the files necessary to instantiate the IP in your design and synthesize it.
Related Information