A newer version of this document is available. Customers should click here to go to the newest version.
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. Chroma Resampler Intel® FPGA IP 10. Clipper Intel® FPGA IP 11. Clocked Video to Full Raster Converter Intel® FPGA IP 12. Color Space Converter Intel® FPGA IP 13. Full Raster to Clocked Video Converter Intel® FPGA IP 14. Full Raster to Streaming Converter Intel® FPGA IP 15. Guard Bands Intel® FPGA IP 16. Mixer Intel® FPGA IP 17. Pixels in Parallel Converter Intel® FPGA IP 18. Scaler Intel® FPGA IP 19. Tone Mapping Operator Intel® FPGA IP 20. Test Pattern Generator Intel® FPGA IP 21. Video Frame Buffer Intel® FPGA IP 22. Video Streaming FIFO Intel® FPGA IP 23. Warp Intel® FPGA IP 24. Design Security 25. Document Revision History for Video and Vision Processing Suite User Guide
16.1. About the Mixer IP
The mixer Intel FPGA IP allows you to overlay video fields from multiple inputs on each other, either with or without alpha blending (transparency).
The mixer supports up to eight inputs (or layers). Layer 0 is the base layer, onto which the IP overlays every other layer (overlay layers). The resolution of the base layer determines the output resolution. Overlay layers can be offset horizontally and vertically within the base layer so that their first pixel overlays at any position within the base layer. Offsets must be such that the full overlay layer image remains inside the confines of the base layer.
The mixer supports both full and lite variants of the Intel FPGA streaming video protocol.
Did you find the information on this page useful?