Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 4/04/2022

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11.3. Clocked Video to Full Raster Converter Block Description

The IP passes the pixel and timing data through unmodified. The AXI4-S based streaming full raster bus encapsulates all the pixel and timing data on a single bus, tData. The clocked video bus is a bundle of multiple single wires for the individual video timing strobes, and a data bus for the pixel data.

The clocked video bus can contain additional sideband signals, such as discrete 16-bit signals for the width and height of the raster. The IP ignores these sideband signals and copies some signals CPU registers. The sideband signals provide backward IO interface compatibility between the IP and legacy Intel clocked video input and clocked video output interfaces.

Figure 25. High-level mapping from the clocked video to full rasterThe figure shows how mapping is a case of concatenating the discrete signals used by the clocked video interface into a single AXI4-S streaming full raster tData bus.

The AXI4-S tUser signal cannot be generated automatically from the clocked video timing signals. The tUser is asserted for true pixels (0,0) in the full video raster, but the location of (0,0) relative to the timing strobes varies by video standard. Therefore, you need either a CPU interface to instruct the tUser logic where to place in the raster the tUser, or the IP is restricted to a single video standard.