Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 4/04/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

23.1.1. Warp IP Features

  • Avalon memory-mapped interface for memory access
  • Fixed 10 bits per color RGB or YUV 4:4:4
  • One or two pixels in parallel
  • Sub-frame latency (transform dependent)
  • Software controlled arbitrary warps up to UHD and easy warp for resource efficient mirroring and rotations up to full HD
  • Maximum image size of 3840x3840
  • Minimum image size of 128x64
  • 600 MHz video and processing clock speeds in Intel Agilex devices

Did you find the information on this page useful?

Characters remaining:

Feedback Message