Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 4/04/2022

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3.2. Latency

You can use the latency information of video and vision processing IPs to predict the approximate latency between the input and the output of your video processing pipeline.

The latency is described using one or more of the following measures:

  • The number of progressive frames or interlaced fields
  • The number of lines when less than a field of latency
  • A number of cycles

For all latency metrics, assume that other functions on the datapath are not stalling the IP and the tready signal is high. If not stated for an IP, the approximate latency from the video data input to the video data output for typical usage modes of the IPs is of the order of a small number of cycles, for example between 1 and 20.