Arria V GZ Avalon-ST Interface for PCIe Solutions: User Guide

ID 683297
Date 12/21/2020
Document Table of Contents

3.2.2. Understanding the Generated Files

Table 10.  Qsys Generation Output Files




Includes the top‑level HDL file for the Hard IP for PCI Express and the .qip file that lists all of the necessary assignments and information required to process the IP core in the Quartus® Primecompiler. Generally, a single .qip file is generated for each IP core. These files are used for Quartus® Primesynthesis.


Includes the HDL files necessary for Quartus® Prime synthesis.


Includes the HDL source files and scripts for the simulation testbench.