Arria V GZ Avalon-ST Interface for PCIe Solutions: User Guide

ID 683297
Date 12/21/2020
Document Table of Contents

15.1. Connecting the Transceiver Reconfiguration Controller IP Core

The Transceiver Reconfiguration Controller IP Core is available for V-series devices and can be found in the Interface Protocols/Transceiver PHY category in the IP Catalog. When you instantiate the Transceiver Reconfiguration Controller the Enable offset cancellation block and Enable PLL calibration options are enabled by default. For Gen3 variants, you should also turn on Enable adaptive equalization (AEQ) block.

A software driver for the Transceiver Reconfiguration Controller IP Core, Altera PCIe Reconfig Driver IP core, is also available in the IP Catalog under Interface Protocols/PCIe. The PCIe Reconfig Driver is implemented in clear text that you can modify if your design requires different reconfiguration functions.

Note: You must include a software driver in your design to program the Transceiver Reconfiguration Controller IP Core.
Figure 54. Altera Transceiver Reconfiguration Controller Connectivity The following figure shows the connections between the Transceiver Reconfiguration Controller instance and the PHY IP Core for PCI Express instance for a ×4 variant.

As this figure illustrates, the reconfig_to_xcvr[ <n> 70-1:0] and reconfig_from_xcvr[ <n> 46-1:0] buses connect the two components. You must provide a 100–125 MHz free‑running clock to the mgmt_clk_clk clock input of the Transceiver Reconfiguration Controller IP Core.

Initially, each lane and TX PLL require a separate reconfiguration interface. The parameter editor reports this number in the message pane. You must take note of this number so that you can enter it as a parameter value in the Transceiver Reconfiguration Controller parameter editor. The following figure illustrates the messages reported for a Gen2 ×4 variant. The variant requires five interfaces: one for each lane and one for the TX PLL.

Figure 55. Number of External Reconfiguration Controller Interfaces

When you instantiate the Transceiver Reconfiguration Controller, you must specify the required Number of reconfiguration interfaces as the following figure illustrates.

Figure 56. Specifying the Number of Transceiver Interfaces for Arria V GZ and Stratix V Devices

The Transceiver Reconfiguration Controller includes an Optional interface grouping parameter. Transceiver banks include six channels. For a ×4 variant, no special interface grouping is required because all 4 lanes and the TX PLL fit in one bank.

Note: Although you must initially create a separate logical reconfiguration interface for each lane and TX PLL in your design, when the Quartus® Prime software compiles your design, it reduces the original number of logical interfaces by merging them. Allowing the Quartus® Prime software to merge reconfiguration interfaces gives the Fitter more flexibility in placing transceiver channels.
Note: You cannot use SignalTap to observe the reconfiguration interfaces.