Arria V GZ Avalon-ST Interface for PCIe Solutions: User Guide

ID 683297
Date 12/21/2020
Document Table of Contents

2.1.7. Compiling the Design in the Qsys Design Flow

To compile the Qsys design example in the Quartus® Prime software, you must create a Quartus® Prime project and add your Qsys files to that project.

  1. Before compiling, you can optionally turn on two parameters in the testbench. The first parameter specifies pin assignments that match those for the Intel Development Kit board I/Os. The second parameter enables the Compliance Base Board (CBB) logic on the development board. In the Gen1 x8 example design, complete the following steps if you want to enable these parameters:
    1. Right-click the APPS component and select Edit.
    2. Turn on Enable FPGA Dev kit board I/Os.
    3. Turn on Enable FPGA Dev kit board CBB logic.
    4. Click Finish.
    5. On the Generate menu, select Generate Testbench System and then click Generate.
    6. On the Generate menu, select Generate HDL and then click Generate. (You can use the same parameters that are specified in Generating the Testbench earlier in this chapter).
  2. In the Quartus® Prime software, click the New Project Wizard icon.
  3. Click Next in the New Project Wizard: Introduction (The introduction does not appear if you previously turned it off.)
  4. On the Directory, Name, Top-Level Entity page, enter the following information:
    1. The working directory shown is correct. You do not have to change it.
    2. For the project name, browse to the synthesis directory that includes your Qsys project, <working_dir>/pcie_de_gen1_x8_ast128/synthesis. Select your variant name, pcie_de_gen1_x8_ast128.v . Then, click Open.
    3. For Project Type select Empty project.
  5. Click Next to display the Add Files page.
  6. Complete the following steps to add the Quartus® Prime IP File ( .qip )to the project:
    1. Click the browse button. The Select File dialog box appears.
    2. In the Files of type list, select IP Variation Files (*.qip).
    3. Click pcie_de_gen1_x8_ast128.qip and then click Open.
    4. On the Add Files page, click Add.
  7. Click Next to display the Device page.
  8. On the Family & Device Settings page, choose the following target device family and options:
    1. In the Family list, select Arria® V GZ.
    2. In the Devices list, select Arria® V GZ All.
    3. In the Available Devices list, select 5AGZME5K2F40C3 .
  9. Click Next to close this page and display the EDA Tool Settings page.
  10. From the Simulation list, select ModelSim ®. From the Format list, select the HDL language you intend to use for simulation.
  11. Click Next to display the Summary page.
  12. Check the Summary page to ensure that you have entered all the information correctly.
  13. Click Finish to create the Quartus® Prime project.
  14. Before compiling, you must assign I/O standards to the pins of the device. Refer to Making Pin Assignments to Assign I/O Standard to Serial Data Pins for instructions.
  15. You must connect the pin_perst reset signal to the corresponding nPERST pin of the device. Refer to the definition of pin_perst in the Reset, Status, and Link Training Signals section for more information.
  16. Next, set the value of the test_in bus to a value that is compatible for hardware testing. In Qsys design example provided, test_in is a top-level port.
    1. Comment out the test_in port in the top-level Verilog generated file.
    2. Add the following declaration, wire[31:0] test_in, to the same top-level Verilog file.
    3. Assign hip_ctrl_test_in = 32'h188.
    4. Connect test_in to hip_ctrl_test_in.
    Refer to the definition of test_in in the Test Signals section for more information about the bits of the test_in bus.
  17. Add the Synopsys Design Constraint (SDC) shown in the following example below to the top‑level design file for your Quartus® Prime project.
  18. To compile your design using the Quartus® Prime software, on the Processing menu, click Start Compilation. The Quartus® Prime software then performs all the steps necessary to compile your design.

Synopsys Design Constraints

create_clock -period “100 MHz” -name {refclk_pci_express}{*refclk_*}

# PHY IP reconfig controller constraints
# Set reconfig_xcvr clock
# Modify to match the actual clock pin name
# used for this clock, and also changed to have the correct period set
create_clock -period "125 MHz" -name {reconfig_xcvr_clk}{*reconfig_xcvr_clk*}

# HIP Soft reset controller SDC constraints
set_false_path -to [get_registers* altpcie_rs_serdes|fifo_err_sync_r[0]]
set_false_path -from [get_registers *sv_xcvr_pipe_native*] -to[get_registers *altpcie_rs_serdes|*]

# Hard IP testin pins SDC constraints
set_false_path -from [get_pins -compatibilitly_mode *hip_ctrl*]

Files Generated for Intel IP Cores

Figure 7. IP Core Generated Files