Arria V GZ Avalon-ST Interface for PCIe Solutions: User Guide

ID 683297
Date 12/21/2020
Document Table of Contents

2.1.5. Understanding Simulation Log File Generation

Starting with the Quartus II 14.0 software release, simulation automatically creates a log file, altpcie_monitor_<dev>_dlhip_tlp_file_log.log in your simulation directory.
Table 8.  Sample Simulation Log File Entries
Time TLP Type Payload (Bytes) TLP Header
17989 RX CfgRd0 0004 04000001_0000000F_01080008
17989 RX MRd 0000 00000000_00000000_01080000
18021 RX CfgRd0 0004 04000001_0000010F_0108002C
18053 RX CfgRd0 0004 04000001_0000030F_0108003C
18085 RX MRd 0000 00000000_00000000_0108000C