Arria V GZ Avalon-ST Interface for PCIe Solutions: User Guide
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5.14.2.1. Physical Layout of Hard IP in Arria V GZ Devices
Refer to Transceiver Architecture in Arria V Devices for comprehensive information on the number of Hard IP for PCIe IP cores available in various Arria V GZ packages.
Refer to Channel Utilization for Data and Clock Routing in Arria V GZ and Stratix V Devices for additional information about channel and PLL utilization.