Arria V GZ Avalon-ST Interface for PCIe Solutions: User Guide

ID 683297
Date 12/21/2020
Document Table of Contents

16.1. Endpoint Testbench

After you install the Quartus® Prime software, you can copy any of the example designs from the <install_dir>/ip/altera/altera_pcie/altera_pcie_hip_ast_ed/example_design directory. You can generate the testbench from the example design as was shown in Getting Started with the Arria® V GZ Hard IP for PCI Express.

This testbench simulates up to an ×8 PCI Express link using either the PIPE interfaces of the Root Port and Endpoints or the serial PCI Express interface. The testbench design does not allow more than one PCI Express link to be simulated at a time. The following figure presents a high level view of the design example.

Figure 57. Design Example for Endpoint Designs

The top-level of the testbench instantiates the following main modules:

  • altpcietb_bfm_top_rp.v: This is the Root Port PCI Express BFM. For more information about this module, refer to Root Port BFM.

In addition, the testbench has routines that perform the following tasks:

  • Generates the reference clock for the Endpoint at the required frequency.
  • Provides a PCI Express reset at start up.

Before running the testbench, you should set the following parameters in <instantiation_name>_tb/sim/<instantiation_name>_tb.v:

  • serial_sim_hwtcl: Set to 1 for serial simulation and 0 for PIPE simulation.
  • enable_pipe32_sim_hwtcl: Set to 0 for serial simulation and 1 for PIPE simulation.