Arria V GZ Avalon-ST Interface for PCIe Solutions: User Guide

ID 683297
Date 12/21/2020
Document Table of Contents

16.4. Root Port Design Example

The design example includes the following primary components:

  • Root Port variation (<qsys_systemname>.
  • Avalon-ST Interfaces (altpcietb_bfm_vc_intf_ast)—handles the transfer of TLP requests and completions to and from the Arria® V GZ Hard IP for PCI Express variation using the Avalon‑ST interface.
  • Root Port BFM tasks—contains the high-level tasks called by the test driver, low‑level tasks that request PCI Express transfers from altpcietb_bfm_vc_intf_ast, the Root Port memory space, and simulation functions such as displaying messages and stopping simulation.
  • Test Driver (altpcietb_bfm_driver_rp.v)—the chaining DMA Endpoint test driver which configures the Root Port and Endpoint for DMA transfer and checks for the successful transfer of data. Refer to the Test Driver Modulefor a detailed description.
Figure 58. Root Port Design Example

You can use the example Root Port design for Verilog HDL simulation. All of the modules necessary to implement the example design with the variation file are contained in altpcietb_bfm_ep_example_chaining_pipen1b.v.

The top-level of the testbench instantiates the following key files:

  • altlpcietb_bfm_top_ep.v— this is the Endpoint BFM. This file also instantiates the SERDES and PIPE interface.
  • altpcietb_pipe_phy.v—used to simulate the PIPE interface.
  • altp cietb_bfm_ep_example_chaining_pipen1b.v—the top-level of the Root Port design example that you use for simulation. This module instantiates the Root Port variation, <variation_name> .v, and the Root Port application altpcietb_bfm_vc_intf _<application_width> . This module provides both PIPE and serial interfaces for the simulation environment. This module has two debug ports named test_out_icm_(which is the test_out signal from the Hard IP) and test_in which allows you to monitor and control internal states of the Hard IP variation.
  • altpcietb_bfm_vc_intf_ast.v—a wrapper module which instantiates either altpcietb_vc_intf_64 or altpcietb_vc_intf_ <application_width> based on the type of Avalon‑ST interface that is generated.
  • altpcietb_vc_intf_ _<application_width> .v—provide the interface between the Arria® V GZ Hard IP for PCI Express variant and the Root Port BFM tasks. They provide the same function as the altpcietb_bfm_vc_intf.v module, transmitting requests and handling completions. Refer to the Root Port BFM for a full description of this function. This version uses Avalon‑ST signaling with either a 64- or 128-bit data bus interface.
  • altpcierd_tl_cfg_sample.v—accesses Configuration Space signals from the variant. Refer to the Chaining DMA Design Examples for a description of this module.

Files in subdirectory <qsys_systemname> /testbench/simulation/submodules:

  • altpcietb_bfm_ep_example_chaining_pipen1b.v—the simulation model for the chaining DMA Endpoint.
  • altpcietb_bfm_driver_rp.v–this file contains the functions to implement the shared memory space, PCI Express reads and writes, initialize the Configuration Space registers, log and display simulation messages, and define global constants.