Arria V GZ Avalon-ST Interface for PCIe Solutions: User Guide

ID 683297
Date 12/21/2020
Document Table of Contents

3.3.1. Timing for Configuration Read to Function 0 for the 256-Bit Avalon-ST Interface

The following timing diagram illustrates a Configuration Read to Function 0 starting at time 60568 ns in the simulation.

Figure 12. Configuration Read to Function 0

The preceding timing diagram illustrates the following sequence of events:

  1. The Application Layer indicates it is ready to receive requests by asserting RxSTReady_o. The RX Avalon-ST interface initiates a Configuration Read, asserting its RxStSop_i and RxStValid_i signals.
  2. At the falling edge of RxStSop_i, the Avalon-MM master interface asserts cfg_rden_o and specifies the address on cfg_addr_o[31:0].
  3. The Function 0 Avalon-MM slave interface asserts cfg_rddavalid_i and drives the data on cfg_rddata_i[31:0].
  4. On the falling edge of cfg_rddavalid_i, the TX interface asserts TxStSop_o and TxStValid_o and drives the data of TxStData_o[255:0]. This is the Completion Request to the host corresponding to its Configuration Read Request.