Arria V GZ Avalon-ST Interface for PCIe Solutions: User Guide

ID 683297
Date 12/21/2020
Document Table of Contents

1.8. Resource Utilization

Because the PCIe protocol stack is implemented in hardened logic, it uses no core device resources (no ALMs and no embedded memory).

Note: Soft calibration of the transceiver module requires additional logic. The amount of logic required depends upon the configuration.