Arria V GZ Avalon-ST Interface for PCIe Solutions: User Guide

ID 683297
Date 12/21/2020
Document Table of Contents

2.1.2. Simulating the Example Design

  1. Start your simulation tool. This example uses the ModelSim® software.
  2. From the ModelSim transcript window, in the testbench directory type the following commands:
    1. do msim_setup.tcl
    2. ld_debug (This command compiles all design files and elaborates the top‑level design without any optimization.)
    3. run -all

The simulation includes the following stages:

  • Link training
  • Configuration
  • DMA reads and writes
  • Root Port to Endpoint memory reads and writes

Disabling Scrambling for Gen1 and Gen2 to Interpret TLPs at the PIPE Interface

  1. Go to <project_directory/<variant>/testbench/<variant>_tb/simulation/submodules/.
  2. Open altpcietb_bfm_top_rp.v.
  3. Locate the declaration of test_in[2:1]. Set test_in[2] = 1 and test_in[1] = 0. Changing test_in[2] = 1 disables data scrambling on the PIPE interface.
  4. Save altpcietb_bfm_top_rp.v.