Arria V GZ Avalon-ST Interface for PCIe Solutions: User Guide

ID 683297
Date 12/21/2020
Document Table of Contents

2.1. Qsys Design Flow

Copy the pcie_de_gen1_x8_ast128.qsys design example from the <install_dir>/ip/altera/altera_pcie/altera_pcie/altera_pcie_hip_ast_ed/example_designs/<dev> to your working directory.

The following figure illustrates this Qsys system.

Figure 6. Complete Gen1 ×8 Endpoint (DUT) Connected to Example Design (APPS)

The example design includes the following components:

  • DUT—This is Gen1 ×8 Endpoint. For your own design, you can select the data rate, number of lanes, and either Endpoint or Root Port mode.
  • APPS—This Root Port BFM configures the DUT and drives read and write TLPs to test DUT functionality. An Endpoint BFM is available if your PCI Express design implements a Root Port.
  • pcie_reconfig_driver_0—This Avalon‑MM master drives the Transceiver Reconfiguration Controller. The pcie_reconfig_driver_0 is implemented in clear text that you can modify if your design requires different reconfiguration functions. After you generate your Qsys system, the Verilog HDL for this component is available as: <working_dir>/<variant_name>/testbench/<variant_name>_tb/simulation/submodules/
  • Transceiver Reconfiguration Controller—The Transceiver Reconfiguration Controller dynamically reconfigures analog settings to improve signal quality. For Gen1 and Gen2 data rates, the Transceiver Reconfiguration Controller must perform offset cancellation and PLL calibration. For the Gen3 data rate, the pcie_reconfig_driver_0 performs AEQ through the Transceiver Reconfiguration Controller.