Arria V GZ Avalon-ST Interface for PCIe Solutions: User Guide

ID 683297
Date 12/21/2020
Document Table of Contents

In single packer per cycle mode, all received TLPs start at the lower 128-bit boundary on a 256-bit Avalon-ST interface. Turn on Enable Multiple Packets per Cycle on the System Settings tab of the parameter editor to change multiple packets per cycle.

Single packet per cycle mode requires simpler Application Layer packet decode logic on the TX and RX paths because packets always start in the lower 128-bits of the Avalon-ST interface. Although this mode simplifies the Application Layer logic, failure to use the full 256-bit Avalon-ST may slightly reduce the throughput of a design.

The following figure illustrates the layout of header and data for a three dword header on a 256‑bit bus with aligned and unaligned data.

256-Bit Avalon-ST tx_st_data Cycle Definition for 3-Dword Header TLP with Qword Addresses