Arria V GZ Avalon-ST Interface for PCIe Solutions: User Guide

ID 683297
Date 12/21/2020
Document Table of Contents

The transceiver derives pclk from the 100 MHz refclk signal that you must provide to the device.

The PCI Express Base Specification requires that the refclk signal frequency be 100 MHz ±300 PPM.

The transitions between Gen1, Gen2, and Gen3 should be glitchless. pclk can be turned off for most of the 1 ms timeout assigned for the PHY to change the clock rate; however, pclk should be stable before the 1 ms timeout expires.

pclk Clock Frequency

Data Rate



250 MHz


500 MHz

The CDC module implements the asynchronous clock domain crossing between the PHY/MAC pclk domain and the Data Link Layer coreclk domain. The transceiver pclk clock is connected directly to the Hard IP for PCI Express and does not connect to the FPGA fabric.