Arria V GZ Avalon-ST Interface for PCIe Solutions: User Guide

ID 683297
Date 12/21/2020
Document Table of Contents

Avalon-ST RX Component Specific Signals




rx_st_mask Input

The Application Layer asserts this signal to tell the Hard IP to stop sending non-posted requests. This signal can be asserted at any time. The total number of non‑posted requests that can be transferred to the Application Layer after rx_st_mask is asserted is not more than 10.

This signal stalls only non-posted TLPs. All others continue to be forwarded to the Application Layer. The stalled non-posted TLPs are held in the RX buffer until the mask signal is deasserted. They are not be discarded. If used in a Root Port mode, asserting the rx_st_mask signal stops all I/O and MemRd and configuration accesses because these are all non-posted transactions.



The decoded BAR bits for the TLP. Valid for MRd, MWr, IOWR, and IORD TLPs. Ignored for the completion or message TLPs. Valid during the cycle in which rx_st_sop is asserted.

Refer to 64-Bit Avalon-ST rx_st_data<n> Cycle Definitions for 4-Dword Header TLPs with Non-Qword Addresses and 128-Bit Avalon-ST rx_st_data<n> Cycle Definition for 3-Dword Header TLPs with Qword Aligned Addresses for the timing of this signal for 64- and 128-bit data, respectively.

The following encodings are defined for Endpoints:

  • Bit 0: BAR 0
  • Bit 1: BAR 1
  • Bit 2: BAR 2
  • Bit 3: BAR 3
  • Bit 4: BAR 4
  • Bit 5: BAR 5
  • Bit 6: Expansion ROM
  • Bit 7: Reserved

The following encodings are defined for Root Ports:

  • Bit 0: BAR 0
  • Bit 1: BAR 1
  • Bit 2: Primary Bus number
  • Bit 3: Secondary Bus number
  • Bit 4: Secondary Bus number to Subordinate Bus number window
  • Bit 5: I/O window
  • Bit 6: Non-Prefetchable window
  • Bit 7: Prefetchable window

For multiple packets per cycle, this signal is undefined. If you turn on Enable multiple packets per cycle, do not use this signal to identify the address BAR hit.



Byte enables corresponding to the rx_st_data. The byte enable signals only apply to PCI Express Memory Write and I/O Write TLP payload fields. When using 64-bit Avalon-ST bus, the width of rx_st_be is 8 bits. When using 128-bit Avalon-ST bus, the width of rx_st_be is 16 bits. This signal is optional. You can derive the same information by decoding the FBE and LBE fields in the TLP header. The byte enable bits correspond to data bytes as follows:

  • rx_st_data[127:120] = rx_st_be[15]
  • rx_st_data[119:112] = rx_st_be[14]
  • rx_st_data[111:104] = rx_st_be[13]
  • rx_st_data[95:88] = rx_st_be[12]
  • rx_st_data[87:80] = rx_st_be[11]
  • rx_st_data[79:72] = rx_st_be[10]
  • rx_st_data[71:64]  = rx_st_be[9]
  • rx_st_data[7:0]    =  rx_st_be[8]
  • rx_st_data[63:56] = rx_st_be[7]
  • rx_st_data[55:48] = rx_st_be[6]
  • rx_st_data[47:40] = rx_st_be[5]
  • rx_st_data[39:32] = rx_st_be[4]
  • rx_st_data[31:24] = rx_st_be[3]
  • rx_st_data[23:16] = rx_st_be[2]
  • rx_st_data[15:8]  = rx_st_be[1]
  • rx_st_data[7:0]    =  rx_st_be[0]

This signal is deprecated.



The IP core generates byte parity when you turn on Enable byte parity ports on Avalon-ST interface on the System Settings tab of the parameter editor. Each bit represents odd parity of the associated byte of the rx_st_datarx_st_data bus. For example, bit[0] corresponds to rx_st_data[7:0] rx_st_data[7:0], bit[1] corresponds to rx_st_data[15:8].



When asserted indicates that the internal RX buffer has overflowed.

For more information about the Avalon-ST protocol, refer to the Avalon Interface Specifications.