Intel Agilex® 7 Embedded Memory User Guide

ID 683241
Date 10/19/2023
Public
Document Table of Contents
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4.4.2. Shift Register (RAM-based) Intel® FPGA IP Features

The Shift Register (RAM-based) Intel® FPGA IP implements a shift register with taps and offers additional features, which include:
  • Selectable RAM block type
  • A wide range of widths for the shiftin and shiftout ports
  • Support for output taps at certain points in the shift register chain
  • Selectable distance between taps