Intel Agilex® 7 Embedded Memory User Guide

ID 683241
Date 10/19/2023
Public
Document Table of Contents
Give Feedback

2.7. Intel Agilex® 7 Embedded Memory Configurations

Table 10.  Supported Embedded Memory Block ConfigurationsThis table lists the maximum configurations supported for the Intel Agilex® 7 embedded memory blocks.
Embedded Memory Block Depth (bits) Programmable Width
MLAB 32 ×16, ×18, or ×20
M20K 512 ×32 or ×40
Note: For simple dual-port only.
1024 ×20
Note: For simple dual-port and true dual-port.
2048 ×10
Note: For simple dual-port, true dual-port, and simple quad-port.
eSRAM 1024 3 x64 3
3 The eSRAM channel depth and width can be programmably reduced to realize power savings. Refer to eSRAM Intel Agilex® FPGA IP section for further details.