Intel Agilex® 7 Embedded Memory User Guide

ID 683241
Date 10/19/2023
Public
Document Table of Contents
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4.3.17. Reset Scheme

During power-up, the registers in the Intel Agilex® 7 devices are in undefined power and reset states. To guarantee correct functionality, reset the FIFO Intel® FPGA IP core upon completion of configuration by asserting either the sclr or aclr signal.