Agilex™ 7 Embedded Memory User Guide

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ID 683241
Date 3/29/2024
Public
Document Table of Contents
Document Table of Contents x
1. Agilex™ 7 Embedded Memory Overview 2. Agilex™ 7 Embedded Memory Architecture and Features 3. Agilex™ 7 Embedded Memory Design Considerations 4. Agilex™ 7 Embedded Memory IP References 5. Agilex™ 7 Embedded Memory Debugging 6. Agilex™ 7 Embedded Memory User Guide Archives 7. Document Revision History for the Agilex™ 7 Embedded Memory User Guide
1. Agilex™ 7 Embedded Memory Overview x
1.1. Agilex™ 7 Embedded Memory Features
2. Agilex™ 7 Embedded Memory Architecture and Features x
2.1. Fabric Network-On-Chip (NoC) in Agilex™ 7 M-Series M20K Blocks 2.2. Byte Enable in Agilex™ 7 Embedded Memory Blocks 2.3. Address Clock Enable Support 2.4. Asynchronous Clear and Synchronous Clear 2.5. Memory Blocks Error Correction Code (ECC) Support 2.6. Agilex™ 7 Embedded Memory Clocking Modes 2.7. Agilex™ 7 Embedded Memory Configurations 2.8. Force-to-Zero 2.9. Coherent Read Memory 2.10. Freeze Logic 2.11. True Dual Port Dual Clock Emulator 2.12. Initial Value of Read and Write Address Registers 2.13. Timing/Power Optimization Feature in M20K Blocks 2.14. Agilex™ 7 Supported Embedded Memory IPs
2.2. Byte Enable in Agilex™ 7 Embedded Memory Blocks x
2.2.1. Byte Enable Controls 2.2.2. Data Byte Output 2.2.3. Byte Enable Behavior
2.5. Memory Blocks Error Correction Code (ECC) Support x
2.5.1. Parity Bit 2.5.2. ECC Parity Flip 2.5.3. ECC Read-During-Write Behavior 2.5.4. Error Correction Code Truth Table
2.6. Agilex™ 7 Embedded Memory Clocking Modes x
2.6.1. Single Clock Mode 2.6.2. Read/Write Clock Mode 2.6.3. Input/Output Clock Mode 2.6.4. Asynchronous/Synchronous Clears in Clocking Modes 2.6.5. Output Read Data in Simultaneous Read/Write 2.6.6. Independent Clock Enables in Clocking Modes
2.7. Agilex™ 7 Embedded Memory Configurations x
2.7.1. Mixed-Width Port Configurations
2.9. Coherent Read Memory x
2.9.1. Forwarding Logic
3. Agilex™ 7 Embedded Memory Design Considerations x
3.1. Consider the Memory Block Selection 3.2. Consider the Concurrent Read Behavior 3.3. Customize Read-During-Write Behavior 3.4. Consider Power-Up State and Memory Initialization 3.5. Reduce Power Consumption 3.6. Avoid Providing Non-Deterministic Input 3.7. Avoid Changing Clock Signals and Other Control Signals Simultaneously 3.8. Advanced Settings in Quartus® Prime Software for Memory 3.9. Consider the Memory Depth Setting 3.10. M20K Embedded Memory Block Input Clock Quality Requirement 3.11. Consider Registering the Memory Output
3.3. Customize Read-During-Write Behavior x
3.3.1. Same-Port Read-During-Write Mode 3.3.2. Mixed-Port Read-During-Write Mode
4. Agilex™ 7 Embedded Memory IP References x
4.1. On Chip Memory RAM and ROM Intel® FPGA IP Cores 4.2. eSRAM Agilex™ FPGA IP 4.3. FIFO Intel® FPGA IP 4.4. Shift Register (RAM-based) Intel® FPGA IP
4.1. On Chip Memory RAM and ROM Intel® FPGA IP Cores x
4.1.1. Release Information for RAM and ROM Intel® FPGA IPs 4.1.2. RAM: 1-PORT Intel® FPGA IP Parameters 4.1.3. RAM: 2-PORT Intel® FPGA IP Parameters 4.1.4. RAM: 4-PORT Intel® FPGA IP Parameters 4.1.5. ROM: 1-PORT Intel® FPGA IP Parameters 4.1.6. ROM: 2-PORT Intel® FPGA IP Parameters 4.1.7. Changing Parameter Settings Manually 4.1.8. RAM and ROM Interface Signals
4.1.7. Changing Parameter Settings Manually x
4.1.7.1. RAM and ROM Parameter Settings
4.2. eSRAM Agilex™ FPGA IP x
4.2.1. Release Information for eSRAM Agilex™ FPGA IP 4.2.2. eSRAM System Features 4.2.3. eSRAM Agilex™ FPGA IP Parameters 4.2.4. eSRAM Agilex™ FPGA IP Interface Signals 4.2.5. eSRAM Timing Diagrams
4.2.2. eSRAM System Features x
4.2.2.1. eSRAM Specifications
4.3. FIFO Intel® FPGA IP x
4.3.1. Release Information for FIFO Intel® FPGA IP 4.3.2. Configuration Methods 4.3.3. Specifications 4.3.4. FIFO Functional Timing Requirements 4.3.5. SCFIFO ALMOST_EMPTY Functional Timing 4.3.6. FIFO Output Status Flag and Latency 4.3.7. FIFO Metastability Protection and Related Options 4.3.8. FIFO Synchronous Clear and Asynchronous Clear Effect 4.3.9. SCFIFO and DCFIFO Show-Ahead Mode 4.3.10. Different Input and Output Width 4.3.11. DCFIFO Timing Constraint Setting 4.3.12. Coding Example for Manual Instantiation 4.3.13. Design Example 4.3.14. Gray-Code Counter Transfer at the Clock Domain Crossing 4.3.15. Guidelines for Embedded Memory ECC Feature 4.3.16. FIFO Intel® FPGA IP Parameters 4.3.17. Reset Scheme
4.3.3. Specifications x
4.3.3.1. Verilog HDL Prototype 4.3.3.2. VHDL Component Declaration 4.3.3.3. VHDL LIBRARY-USE Declaration 4.3.3.4. HDL Code from Parameterizable Macros Template 4.3.3.5. FIFO Signals 4.3.3.6. FIFO Parameter Settings
4.3.8. FIFO Synchronous Clear and Asynchronous Clear Effect x
4.3.8.1. Recovery and Removal Timing Violation Warnings when Compiling a DCFIFO
4.3.11. DCFIFO Timing Constraint Setting x
4.3.11.1. Embedded Timing Constraint 4.3.11.2. User Configurable Timing Constraint
4.3.11.2. User Configurable Timing Constraint x
4.3.11.2.1. SDC Commands
4.4. Shift Register (RAM-based) Intel® FPGA IP x
4.4.1. Release Information for Shift Register (RAM-based) Intel® FPGA IP 4.4.2. Shift Register (RAM-based) Intel® FPGA IP Features 4.4.3. Shift Register (RAM-based) Intel® FPGA IP General Description 4.4.4. Shift Register (RAM-based) Intel® FPGA IP Parameter Settings 4.4.5. Shift Register Ports and Parameters Setting
1. Agilex™ 7 Embedded Memory Overview
2. Agilex™ 7 Embedded Memory Architecture and Features
3. Agilex™ 7 Embedded Memory Design Considerations
4. Agilex™ 7 Embedded Memory IP References
5. Agilex™ 7 Embedded Memory Debugging
6. Agilex™ 7 Embedded Memory User Guide Archives
7. Document Revision History for the Agilex™ 7 Embedded Memory User Guide

2.11. True Dual Port Dual Clock Emulator

The true dual port (TDP) dual clock emulator feature emulates a TDP dual clock mode. This feature provides backward compatibility with Arria® 10 devices, which supports TDP dual clock mode.

This feature is supported only in the following conditions:

  • Two read/write ports operation mode.
  • Customize clocks for A and B ports clocking mode.
Note: You must turn on Emulate TDP dual clock mode to enable the TDP dual clock emulator feature in the parameter editors of the dual-port RAM IP core. Refer to RAM: 2-PORT Intel FPGA IP Parameter Settings for more information about how to enable this feature.

The TDP dual clock emulator consists of two DCFIFOs and a single RAM block. The DCFIFO handles clock domain crossing (CDC) issues for the control signals and is a temporary buffer for data storage before and after being processed by the RAM block.

Due to the non-deterministic latency caused by different clock frequencies, a valid signal is introduced to identify whether the output data is valid. When the valid signal is asserted, it indicates that you should adhere to the correct output data. If the valid signal is de-asserted, discard the output data.

The clock connection to Port A must be a slow clock (clock A) and the clock connection to Port B must be a fast clock (clock B), with a clock frequency ratio of clock B divided by clock A is greater than or equal to seven.

The DCFIFO depth follows the RAM depth that is set in the dual-port RAM IP. You may change the DCFIFO depth manually through the design file after the HDL generation in the RAM IP Parameter Editor. The DCFIFO depth must be greater than the clock frequency ratio of clock B divided by clock A to ensure the emulated TDP dual clock mode works properly. For example, if the ratio of Clock B frequency/Clock A frequency is 10, the minimum DCFIFO depth must be 16 (2^4) or above.

When you engage the TDP dual clock emulator feature, port A and port B will have different latency. The latency for port A decreases as the difference between the two clock frequencies increase, with a minimum latency of five clock cycles. Port B latency is fixed to two clock cycles, with the output registers always enabled for this configuration.

The following figures show the timing diagrams for the TDP dual clock emulator feature.

Figure 16. Output Condition of Port A
Figure 17. Output Condition of Port B
Figure 18. Read-During-Write Condition of Port A
Figure 19. Read-During-Write Condition of Port B
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